The present invention relates, in general to power interconnections inside microprocessor packages and other very large scale integrations and more particularly to use of power and ground distribution planes.
Deep sub-micron dimensions, multi-gigahertz clock frequencies, and transistor counts in the tens of millions are becoming commonplace in today""s microprocessors and other very large scale integrations (VLSI""s). Historically, the dominant performance-limiting characteristic associated with VLSI circuits was transistor switching speed. Now, however, a host of new design issues have emerged, among them, the need for clean power and ground distribution to switching devices. Impedances in the power and ground distribution networks, and crosstalk between neighboring paths in the networks are key issues that can lead to system instability and limit overall performance of a processor or other VLSI design. Therefore, in order to further increase VLSI performance, classical power and ground distribution networks may not be suitable.
Traditional high performance power and ground distribution networks can be divided into two types. The first type consists of power and ground grids, where a number of equal-width tracks form finely meshed orthogonal grids on all layers of a multi-layer VLSI package. There are usually grids for power (Vdd) and ground (Grd). While a power and ground grid configuration provides relatively simple design and other beneficial characteristics, it suffers from the key disadvantage of consuming a significant portion of the available space on the chip. In today""s processors it is not uncommon to use 25% to 40% of all usable interconnect space (also termed routing space) for power and ground distribution grids.
The second type of power and ground distribution network consists of separate distribution planes. In this configuration, two entire layers of the multi-layer VLSI package are dedicated to power distribution. Typically one layer is used for Vdd and one for ground. The two distribution planes can be separated by one or more layers of signal nets, and are often bordered above and below by additional layers of signal nets or insulating substrates. Power distribution planes have clear advantages over power grids in that they reduce inductance by providing shorter and more direct current paths. Thus, many advanced high-power processors and VLSI devices favor planar designs
The prior art power distribution planes are generally interspersed with a regular pattern of insulating regions. FIG. 1 depicts such a conventional power distribution plane 100 with conductive paths 120 and insulating regions 140. In the traditional art, the insulating regions are created in square or rectangular shapes for ease of manufacture.
Insulating regions serve two primary purposes. First, they allow construction of limited-width conductive paths. Due to aspects of the manufacturing process, it is easier to construct conductors of a limited width than a solid plane. Thus, a matrix pattern is favored. Secondly, the insulating regions provide a convenient area to locate pass-through vias, pathways that connect the signal nets above the plane to the signal nets below the plane. These vias take up a significant portion of the power distribution plane area since there is often need for a large number of interconnections. The insulating regions conveniently accommodate these vias, avoiding the need to intersperse them throughout the conductive regions.
Despite their improvement over grids, classical plane layouts with rectangular insulating regions still have key shortcomings. It would be desirable to decrease the impedance of the current paths. High path impedance promotes crosstalk between switching devices driven by the power distribution plane. In a typical crosstalk situation, a change in a first switching device may be reflected as a bounce or delay in other switching devices. This occurs when current flowing to or from a first switching device in the distribution plane shares a section of conductive path with current flowing to or from other devices. The higher the impedance along such a shared path the more electromagnetic (inductive) coupling between the current flows. When the first switching device changes state a fluctuation is thus induced in the current supplied to the other switching is devices.
Typically, a VLSI device is designed to expect, and tolerate, voltage fluctuations of about 5% to 10%. However, if the voltage exceeds this tolerance, speed-critical devices will be slowed. It is possible that the device will perform properly in most operations, but fail under certain execution sequences, since the coupling depends on which switching devices are being activated, which in turn depends on the currently executed instructions.
High impedance can be caused by a special phenomenon related to orthogonal corners and boundaries. This phenomenon causes higher impedance when current flows around right-angle corners than around lesser exterior angle corners. Electromagnetic fields become concentrated at sharp bends in a current path, such as the bend made by a ninety degree corner. In such a bend, more electromagnetic flux lines intersect the path of the current flow along a straight portion of conductive path, increasing the local impedance. Therefore it would be highly desirable to minimize the use of ninety-degree corners in a distribution plane design.
The present invention comprises a layout for power and ground planes that can be employed in multi-layer VLSI packages. The power and ground planes are constructed as a matrix of conductive paths surrounding hexagonal or similarly shaped insulating regions.
The use of a hexagonal pattern mitigates crosstalk in signal nets generated by coupling in the power and/or ground distribution planes. With a hexagonal plane pattern for example, there is an increased probability that a low impedance direct line current path, one without corners, will be available to a current flow. While prior art orthogonal designs provided only four primary directions of conductor paths, the hexagonal configuration increases this number to six. Secondly, the largest exterior angle current must deflect around in a hexagonal configuration is sixty degrees, as opposed to ninety degrees in the prior art. This advantageously avoids increased impedance at right-angle corners, a phenomenon caused by electromagnetic field concentrations caused by right angles and other sharp bends in a conductor path.